A prior art fuse trim circuit used in low cost devices is shown in FIG. 1. The prior art circuit of FIG. 1 includes fuse 10, fuse pad 12, V.sub.SS ' pad 14, V.sub.SS pad 16, resistor 18, current source 20, inverters 22 and 24, supply voltage V.sub.DD, and output node 26. Only one bit is shown in FIG. 1. In FIG. 1, output node 26 may be routed to a voltage reference or possibly a trim DAC (digital-to-analog converter) for an amplifier in order to trim the offset voltage. The output voltage of the cell is approximately zero volts (V.sub.SS). This is true because the current source 20 is designed to put out a maximum of 1 .mu.A, which is only 100 .mu.V drop across the fuse 10. This voltage will be interpreted by the first inverter 22 as a logic "zero" so the output of inverter 22 will be a logic "one" (the voltage will be equal to V.sub.DD). Then the output of inverter 24 will be a logic "zero", the same as the fuse pad 12 but buffered. In order to change the state of the fuse cell, the resistance of the fuse 10 must be changed. This is accomplished by holding the V.sub.SS ' pad 14 at zero volts and raising the voltage on the fuse pad 12 to approximately 6 volts by means of external probes. The 6 volts across the poly silicon fuse resistor 10 (approximately 100 ohms) will cause Joule heating (i.sup.2 R) due to the current flow which will melt the fuse 10. The melting will be severe enough to open circuit the fuse 10. Another way of saying this is that the fuse resistance becomes infinite. With time some fuses may re-grow so that their resistance will become finite but large (greater than 10 M ohms). Even if the fuses regrow, the voltage across them will be V.sub.fuse .gtoreq.I.sub.s R.sub.fuse .gtoreq.1 .mu.A*10 M ohms&gt;10 V which is larger than the supply voltage, therefore the output will be at V.sub.DD. This then corresponds to a logic "one", and will be buffered by the two inverters as a logic "one" output.
The normal way to determine which fuses to "blow" (blowing a fuse means to force current through it until it melts), is to force the fuse Pad 12 to a voltage less than that necessary to "blow it" but large enough to trip inverter 22. With special design of the inverter trip point, this voltage can be less than two volts. However, the voltage cannot be too low or the logic noise immunity will be a problem for "zero" outputs. Using probes to force the voltage on each fuse pad 12 relative to V.sub.SS ', different logical codes can be tried until the right value is determined. Then the fuses that must be "blown" to get logic "ones" can be stressed with 6 to 6.5 volts. What has been found in production is that when a fuse is pre-stressed with approximately 2 volts to determine the right code, then 6 to 6.5 volts does not reliably blow the fuse. It requires 12 to 13 volts. When designs were done in 10 volt CMOS processes, this was possible because the maximum allowable voltage was 13.5 volts. With 5 volt CMOS processes, the maximum allowable voltage is 7.5 volts. Therefore, once stressing a fuse, it cannot be blown reliably in the allowed maximum voltage of the process. The fuse can reliably be blown with 13 volts, but this may cause a reliability problem by over stressing other circuits on the chip.
Some prior art circuits accomplish no prestress, but are very complex. These circuits require a special test mode along with special hardware and test code to implement this function. The extra on chip circuits include read/write registers or SRAM memory, muxes, and a complex differential fuse cell.